The Xilinx DDR4 controller is high performance (2667Mbps in UItraScale+) and supports a wide range of configurations from low cost components to dense 128GB RDIMMs.
Product Description
The Xilinx DDR4 core can generate a full controller or phy only for custom controller needs. The controller will run up to 2400Mbps in UltraScale and 2667Mbps in UltraScale+. The controller is configurable through the IP catalog. The controller will support data widths from 8b to 80b and multiple memory types including components, UDIMM, SODIMM, RDIMMs, and LRDIMMs. Comprehensive in system testing across PVT corners is done to ensure first time success. Additional debug capabilities are provided like the Advanced Traffic Generator which allows in system testing with PRBS or custom traffic patterns to isolate bit errors on the read or write side. A powerful simulation environment allows you to quickly calculate efficiency based on your traffic patterns. Simple tweaks to the controller settings can help tune and find the best efficiencies.
Key Features and Benefits
- Component support for interface width of 8 to 80 bits (RDIMM, UDIMM, and SODIMM support)
- 128 GB density device support
- x4, x8, and x16 device support
- 8:1 DQ:DQS ratio support for x8 and x16 devices
- 4:1 DQ:DQS ratio support for x4 devices
- Dual slot support for DDR4 DIMMs
- 8-word burst support
- Support for 9 to 24 cycles of column-address strobe (CAS) latency (CL)
- Self-Refresh and Save-Restore
- ODT / DBI support
- Support for 9 to 18 cycles of CAS write latency
- Write leveling support for DDR4 (fly-by routing topology required component designs)
- JEDEC-compliant DDR4 initialization support
- Source code delivery in Verilog
- 4:1 memory to FPGA logic interface clock ratio
- Open, closed, and transaction based pre-charge controller policy
- Interface calibration and training information available through the Vivado hardware manager
https://usermanual.wiki/m/5eacedeb4de73b50143247cfb00cc485e96da9fdf2c82c1cdccb0861045f3d10
UltraScale Architecture-Based FPGAs Memory IP v1.4 LogiCORE IP Product Guide
usermanual.wiki
이거 다 하려고 하지 말고
교육장에서 어떻게 가르칠지에 대해 역공학하기
'적극적 생각 > FPGA' 카테고리의 다른 글
| 0717 - 섹션3 - AXI4Lite (0) | 2022.07.17 |
|---|---|
| vivado ver issue (0) | 2022.07.17 |
| SSD에서의 PCIe 4.0의 역할 (0) | 2022.07.16 |
| gigglehd - news 0716 (0) | 2022.07.16 |
| gigglehd - xilinx, zynq, zybo (0) | 2022.07.16 |