`timescale 1ns / 1ps
module reg_with_load(clk, load, d_in, d_out);
input load;
input [3:0]d_in;
input clk;
output [3:0]d_out;
reg [3:0]d_out;
always @(posedge clk) begin
if(load==1) begin
d_out<= d_in;
end
end
endmodule
`timescale 1ns / 1ps
module reg_with_load(clk, load, d_in, d_out);
input clk;
input load;
input [3:0]d_in;
output [3:0]d_out;
reg [3:0]d_out;
always @(posedge clk) begin
case(load)
1'b1 : d_out <= d_in;
default : d_out <= d_out;
end
endmodule
`timescale 1ns / 1ps
module tb_reg_with_load();
reg load;
reg [3:0]d_in;
reg clk;
wire [3:0]d_out;
reg_with_load reg_with_load(clk, load, d_in, d_out);
always #5 clk=~clk;
initial begin
clk=1'b0; d_in=4'b0000; load=1'b1; #1
d_in=4'b0001; #10
d_in=4'b0010; #10
d_in=4'b0011; #10
d_in=4'b1111; #10
d_in=4'b0000; load=1'b0; #10
d_in=4'b0001; #10
d_in=4'b0010; #10
d_in=4'b0011; #10
d_in=4'b1111; #10
$finish;
end
endmodule
